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| Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Features s s Description The Lucent Technologies Microelectronics Group T7570 Programmable PCM Codec with Hybrid-Balance Filter is a programmable PCM codec with an internal hybrid-balance network filter. It provides analog-to-digital and digital-to-analog conversion, as well as the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed (TDM) system. Programmable features include transmit gain setting over a 19.4 dB range and receive gain setting over a 19.4 dB range. An internal filter can be programmed to provide hybrid balancing over a wide range of loop impedances for both active and transformer subscriber line interface circuits (SLIC). The device is programmed over a low pin-count, standard, serial, microprocessor-control interface. A 6-pin parallel input/output latch is provided to control interface circuits. Each of these pins can be individually programmed to be an input or an output. The T7570 is fabricated by using a low-power CMOS technology, requires a single 5 V supply, and is available in a 28-pin PLCC package for surface mounting. Programmable internal hybrid-balance network Programmable transmit gain -- 19.4 dB range, 0.1 dB step size Programmable receive gain -- 19.4 dB range, 0.1 dB step size Dual-programmable PCM interface -- Up to 64 time slots per frame -- Variable data rate (64 kHz to 4.096 MHz) -- Two timing modes Programmable -law or A-law companding 300 drive receive amplifier Analog and digital loopbacks On-chip sample-and-hold, autozero, and precision voltage reference Single 5 V power supply Latch-up free, low-power CMOS technology -- 70 mW typical operating power dissipation -- 1.5 mW typical standby power dissipation Serial microprocessor-control interface 6-pin parallel I/O latch TTL- and CMOS-compatible digital I/O Meets or exceeds D3/D4 (as per Lucent PUB 43801), ITU-T (formerly CCITT) G.711--G.714, and LSSGR requirements Operating temperature range: -40 C to +85 C s s s s s s s s s s s s s T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Table of Contents Content Page Features ...................................................................................................................................................................1 Description ...............................................................................................................................................................1 Pin Information .........................................................................................................................................................3 Functional Description ..............................................................................................................................................5 Powerup Initialization ............................................................................................................................................5 Powerdown State ..................................................................................................................................................5 Transmit Filter and Encoder ..................................................................................................................................5 Decoder and Receive Filter ..................................................................................................................................6 PCM Interface .......................................................................................................................................................6 Serial Control Port ................................................................................................................................................6 Programmable Functions ......................................................................................................................................7 Hybrid-Balance Filter ..........................................................................................................................................11 Programming the Filter .......................................................................................................................................12 Absolute Maximum Ratings ....................................................................................................................................13 Handling Precautions .............................................................................................................................................13 Electrical Characteristics ........................................................................................................................................14 dc Characteristics ...............................................................................................................................................14 Transmission Characteristics ..................................................................................................................................15 Timing Characteristics ............................................................................................................................................20 Applications ............................................................................................................................................................25 Outline Diagrams ....................................................................................................................................................26 28-Pin PLCC .......................................................................................................................................................26 Ordering Information ...............................................................................................................................................27 2 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Description (continued) AZ VFXI TRANSMIT FILTER ENCODER TX REGISTER DIGITAL LOOPBACK DX0 DX1 TSX0 TSX1 FSX BCLK FSR DR0 DR1 HYBRID BALANCE FILTER ANALOG LOOPBACK VREF TIME-SLOT ASSIGNMENT RX REGISTER VFRO RECEIVE FILTER DECODER MCLK MR IL5 IL4 IL3 IL2 IL1 IL0 INTERFACE LATCHES CONTROL REGISTER CS CCLK CO CI 5-2786 (C) Figure 1. Block Diagram Pin Information VFRO GND VFXI VDD 27 NC NC IL0 26 25 24 23 T7570 --- ML2 22 21 20 19 12 13 14 15 16 17 18 1 NC IL3 IL2 FSR DR1 DR0 CO 5 6 7 8 9 10 11 28 3 4 2 IL1 IL4 IL5 FSX TSX1 TSX0 DX1 CCLK MR BCLK MCLK DX0 CS CI 5-2787 (C) Figure 2. Pin Diagram Lucent Technologies Inc. 3 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Pin Information (continued) Table 1. Pin Description Pin 1 2 Symbol GND VFRO Type -- O Name/Description Ground. All analog and digital signals are referenced to this pin. Receive Analog Power Amplifier Output. This pin can drive load impedances as low as 300 . PCM data received on the assigned DR pin is decoded and appears at this output as a voice-frequency signal. No Connect. Connections may be made to or traces may be routed through this pin. No Connects. Do not make connections to or route traces through pins 4 and 5. Interface Latch I/O. These pins can be individually programmed as inputs or outputs as determined by the state of the corresponding bits in the latch direction register (LDR). For pins configured as inputs, the logic state sensed on each input is latched into the interface latch register (ILR) whenever control data is written to the T7570, and the information is shifted out on the CO pin. When configured as outputs, control data written into the ILR appears at the corresponding IL pins. Receive Frame-Sync Input. A pulse or square-wave waveform with an 8 kHz repetition rate is applied to this input to define the start of the receive time slot assigned to this device (nondelayed frame mode), or the start of the receive frame (delayed frame mode using the internal time-slot assignment counter). Receive PCM Inputs. These receive data input(s) are inactive except during the assigned receive time slot of the assigned port when the receive PCM data is shifted in on the falling edges of BCLK. Control Output. Serial control information is shifted out from the T7570 on this pin when CS is low. It can be connected to CI if required. Control Input. Serial control information is shifted into the T7570 on this pin when CS is low. It can be connected to CO if required. Control Clock. This clock shifts serial control information into CI or out from CO when the CS is low, depending on the current instruction. CCLK can be asynchronous with the other system clocks. Chip Select (Active-Low). When this pin is low, control information can be written into or read from the T7570 via the CI and CO pins. Master Reset. This logic input must be pulled low for normal operation of the T7570. When pulled momentarily high (at least 1 s), all programmable registers in the device are reset to the states specified under powerup initialization. Bit Clock Input. This pin shifts PCM data into and out of the DR and DX pins. BCLK can vary from 64 kHz to 4.096 MHz in 8 kHz increments and must be synchronous with MCLK at the start of each frame. MCLK can be used as BCLK. Master Clock. The master-clock input is used by the switched capacitor filters and the encoder and decoder sequencing logic. It must be 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK at the start of each frame. Transmit PCM Output. These transmit-data, high-impedance state outputs remain in the high-impedance state except during the assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted out on the rising edges of BCLK. Backplane Line Driver Enable (Active-Low). Normally, these open-drain outputs are floating in a high-impedance state. When a time slot is active on one of the DX outputs, the appropriate TS X output pulls low to enable a backplane line driver. 3 4 5 6 7 NC NC IL3 IL2 -- -- I/O I/O 8 FSR I 9 10 11 12 13 DR1 DR0 CO CI CCLK I I O I I 14 15 CS MR I I 16 BCLK I 17 MCLK I 18 19 DX0 DX1 O O 20 21 TS X0 TS X1 O O 4 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Pin Information (continued) Table 1. Pin Description (continued) Pin 22 Symbol FSX Type I Name/Description Transmit Frame-Sync Input. A pulse or square-wave waveform with an 8 kHz repetition rate is applied to this input to define the start of the transmit time slot assigned to this device (nondelayed frame mode) or the start of the transmit frame (delayed frame mode using the internal time-slot assignment counter). If only the receive channel is being used, it is still necessary to apply the transmit framesync every frame. Interface Latch. See pin 6. 23 24 25 26 27 28 IL5 IL4 IL1 IL0 VDD VFXI I/O I/O I/O I/O -- I 5 V 5% Power Supply. Transmit Analog High-Impedance Input. Voice-frequency signals present on this input are encoded as an A-law or -law PCM bit stream and are shifted out on the selected DX pin. Functional Description Powerup Initialization When power is first applied, powerup reset circuitry initializes the T7570 and puts it into the powerdown state. The gain control registers for the transmit and receive gain sections are programmed to off, the hybridbalance circuit is turned off, the power amp is disabled, and the device is in the nondelayed timing mode. The latch direction register (LDR) is preset with all IL pins programmed as inputs, placing the interface pins in a high-impedance state. The CI is ready for the first control byte of the initialization sequence. Other initial states in the control register are indicated in the Control Register Instruction section under Programmable Functions. A reset to these same initial conditions can also be forced by driving the MR pin momentarily high for at least 1 s. This can be done either on powerup or powerdown. For normal operation, this pin must be pulled low. The desired modes for all programmable functions can be initialized via the serial control port prior to a powerup command. control instructions into the serial control port with the P bit set to 1, as indicated in Table 2. The powerdown instruction can be included within any other instruction code. It is recommended that the chip be powered down before executing any instructions. In the powerdown state, all nonessential circuitry is deactivated and the DX0 and DX1 outputs are in the highimpedance condition. The coefficients stored in the hybrid-balance circuit and the gain control registers, the data in the LDR and ILR, and all control bits remain unchanged in the powerdown state unless changed by writing new data via the serial control port, which remains active. The outputs of the interface latches also remain active, maintaining the ability to monitor and control interface circuits like a SLIC. Transmit Filter and Encoder The transmit section input, VFXI, provides a highimpedance load to the line-interface circuit. The input signal is summed with the internal hybrid cancellation signal. The resulting signal is the input to a programmable gain or attenuation amplifier that is controlled by the contents of the transmit gain register (see Programmable Functions section). The signal is then passed through an antialiasing filter followed by a fifth-order, low-pass and third-order, high-pass, switched-capacitor filter. After the filter, the A/D converter translates the signal into PCM data for transmission. The A/D Powerdown State Following a period of activity in the powerup state, the powerdown state can be entered by writing any of the Lucent Technologies Inc. 5 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 mit time slot, the selected DX0/1 output shifts data out from the PCM register on the rising edges of BCLK. TS X0 (or TS X1 as appropriate) also pulls low for the first 7.5 bit times of the time slot to control the highimpedance state enable of a backplane line driver. Serial PCM data is shifted into the selected DR0/1 input during each assigned receive time slot on the falling edges of BCLK. DX0 or DX1 and DR0 or DR1 are selectable on the T7570 (see the Port Selection section under Programmable Functions). Functional Description (continued) Transmit Filter and Encoder (continued) converter has a compressing characteristic according to the standard ITU-T A- or -coding laws selected by a control instruction (see Tables 2 and 3). A precision onchip voltage reference helps ensure accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters, or the comparator is canceled by an internal autozero circuit. Serial Control Port Decoder and Receive Filter PCM data is shifted into the decoder's receive PCM register via the DR0 or DR1 pin during the selected time slot on eight falling edges of BCLK. The decoder consists of an expanding digital-to-analog convertor with either A- or -law decoding characteristic, which is selected by the same control instruction used to select the encode law. Following the decoder is a fifth-order, low-pass, switched-capacitor filter with Sin(x)/x correction for the 8 kHz sample and hold. A programmable gain amplifier that is set by writing to the receive gain register is included, followed by a power amplifier capable of driving a 300 load to 4.0 V peak to peak. Programmable register instructions (Table 2) are written into or read back from the T7570 via the serial control port consisting of the control clock (CCLK), the serial data input (CI) and output (CO), and the chipselect input ( CS ) (see Figure 6). All instructions require 2 bytes, with the exception of a single-byte powerup/powerdown command. The bits in byte 1 are defined as follows: bit 7 specifies powerup or powerdown; bits 6, 5, 4, and 3 specify the register address; bit 2 specifies whether the instruction is a read or a write; bit 1 specifies a one- or two-byte instruction; and bit 0 is not used. To shift control data into the T7570, CCLK must be pulsed high eight times while CS is low. Data on the CI input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded and can indicate that a second byte of control data follows. This second byte can either be defined by a second byte wide CS pulse or can follow the first contiguously; it is not mandatory for CS to return high between the first and second control bytes. At the end of the eighth CCLK pulse in the second control byte, the data is loaded into the appropriate programmable register. CS can remain low continuously when programming successive registers, if desired. However, CS should be set high when no data transfers are in progress. To read back interface latch data or status information from the T7570, the first byte of the appropriate instruction, as defined in Table 2, is strobed in during the first CS pulse. CS must then be taken low for a further eight CCLK cycles, during which the data is shifted onto the CO pin on the rising edges of CCLK. When CS is high, the CO pin is in the high-impedance state, enabling the CO pins of many devices to be multiplexed together. PCM Interface The FSX and FSR frame-sync inputs determine the beginning of the 8-bit transmit and receive time slots, respectively. They can have any duration from a single cycle of BCLK high to one MCLK period low. Two different relationships can be established between the frame-sync inputs and the actual time slots on the PCM buses by setting bit 3 in the control register (see Table 3). Nondelayed data mode is similar to longframe timing of other codecs for which time slots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use delayed-data mode in which each FS input must be high at least a half-cycle of BCLK earlier than the time slot. The timeslot assignment circuit on the device can only be used with delayed-data timing. The time-slot assignment capability of this device is a subset of the Lucent concentration highway interface. The beginning of the first time slot in a frame is identified by the appropriate FS input. The actual transmit and receive time slots are then determined by the internal time-slot assignment counters. Transmit and receive frames and time slots can be skewed from each other by any number of BCLK cycles by offsetting FSR and FSX. During each assigned trans6 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter included with the last programming instruction or in a separate single-byte instruction. When the powerup or powerdown control is entered as a single-byte instruction, bit 1 must be 0. When a powerup command is given, all deactivated circuits are activated, but the PCM outputs, DX0 and DX1, remain in the high-impedance state until the second FSX pulse after powerup. Control Register Instruction The first byte of a read or write instruction to the control register is as shown in Table 2. The second byte has the bit functions shown in Tables 3, 5, 6, 7, 8, and 9. Functional Description (continued) Programmable Functions Any of the programmable registers can be modified while the device is powered up or down. Powerup/Powerdown Control Following powerup initialization, powerup and powerdown control can be accomplished by writing any of the control instructions listed in Table 2 into the T7570, with the P bit set to 0 for powerup or 1 for powerdown. Normally, it is recommended that all programmable functions be initially programmed while the device is powered down. Power-state control can then be Table 2. Programmable Register Instructions Function PDN 7 P P P P P P P P P P P P P P P P P P P P P 6 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Byte 1 Address 5 X 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 4 X 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 3 X 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Byte 2 R/W 2 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 X X X X X X X X X X X X X X X X X X X X X DATA None See Table 3. See Table 6. See Table 5. See Table 9. See Table 8. These bits are defined by the Lucent T7570 hybridbalance software program. Contact your Lucent-ME Account Representative for a copy of this software. See Table 7. (receive instruction) See Table 7. (transmit instruction) Single-byte Powerup/Powerdown Write Control Register Read Control Register Write Interface Latch Register Read Interface Latch Register Write Latch Direction Register Read Latch Direction Register Write Receive Gain Register Read Receive Gain Register Write Transmit Gain Register Read Transmit Gain Register Write Hybrid-balance Register 1 Read Hybrid-balance Register 1 Write Hybrid-balance Register 2 Read Hybrid-balance Register 2 Write Hybrid-balance Register 3 Read Hybrid-balance Register 3 Write Receive Time Slot/Port Read Receive Time Slot/Port Write Transmit Time Slot/Port Read Transmit Time Slot/Port Notes: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI and CO pins. X = don't care. P is the powerup/down control bit (0 = powerup, 1 = powerdown); see Powerup/Powerdown Control section. Other register address codes are invalid and should not be used. Lucent Technologies Inc. 7 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Functional Description (continued) Programmable Functions (continued) Control Register Instruction (continued) Table 3. Control Register Byte 2 Functions 7 F1 0 0 1 1 -- -- -- -- -- -- -- -- -- -- 6 F0 0 1 0 1 -- -- -- -- -- -- -- -- -- -- Bit Number and Name 5 4 3 2 MA IA DN DL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 X -- -- 1 0 -- -- 1 1 -- -- -- -- 0 -- -- -- 1 -- -- -- -- 0 -- -- -- 1 -- -- -- 0 -- -- -- -- -- -- -- -- 1 AL -- -- -- -- -- -- -- -- -- 0 X 1 -- -- 0 PP -- -- -- -- -- -- -- -- -- -- -- -- 0 1 Function Reserved MCLK = 1.536 MHz or 1.544 MHz MCLK = 2.048 MHz* MCLK = 4.096 MHz -law* A-law, Including Even Bit Inversion A-law, No Even Bit Inversion Delayed Data Timing Nondelayed Data Timing* Normal Operation* Digital Loopback Analog Loopback Power Amp Enabled in Powerdown Power Amp Disabled in Powerdown* * State at powerup initialization (bit 4 = 0). Table 4. Coding Law Conventions -Law MSB LSB 10000000 11111111 00000000 True A-Law With Even Bit Inversion MSB LSB 10101010 11010101 00101010 A-Law Without Even Bit Inversion MSB LSB 111111111 10000000 01111111 VIN VIN = + Full Scale VIN = 0 V VIN = - Full Scale Note: The MSB is always the first PCM bit shifted in or out of the T7570. Master Clock Frequency Selection A master clock must be provided to the T7570 for operation of the filter and coding/decoding functions. The MCLK frequency must be either 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK at the start of each frame. Bits F0 and F1 (see Table 3) must be set during initialization to select the correct internal divider. Coding Law Selection Bits MA and IA in Table 3 permit the selection of -law coding or A-law coding, with or without even bit inversion. 8 Analog Loopback The analog loopback mode is entered by setting the AL and DL bits in the control register as shown in Table 3. In the analog loopback mode, the transmit input VFXI is isolated from the input pin and internally connected to the VFRO output, forming a loop from the receive PCM register back to the transmit PCM register. The VFRO pin remains active, and the programmed settings of the transmit and receive gains remain unchanged; therefore, care must be taken to ensure that overload levels are not exceeded anywhere in the loop. It is recommended that the hybrid-balance filter be disabled during analog loopback. Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter It is recommended that during initialization, the state of IL pins to be configured as outputs should be programmed first, followed immediately by the LDR. Table 6. Interface Latch Data Bit Order Bit Number 7 D0 6 D1 5 D2 Bit Number 4 3 D3 D4 2 D5 1 X 0 X Functional Description (continued) Programmable Functions (continued) Digital Loopback The digital loopback mode is entered by setting the AL and DL bits in the control register as shown in Table 3. This mode provides another stage of path verification by enabling data written into the receive PCM register to be read back from that register in any transmit time slot at DX0/1. In digital loopback mode, the decoder remains functional and outputs a signal at VFRO. If this is undesirable, the receive output can be disabled by programming the receive gain register to all 0s. Interface Latch Directions Immediately following powerup, all interface latches assume they are inputs and, therefore, all IL pins are in a high-impedance state. Each IL pin can be individually programmed as a logic input or output by writing the appropriate instruction to the LDR (see Tables 2 and 5). For minimum power dissipation, unconnected latch pins should be programmed as outputs. Bits L5--L0 must be set by writing the specified instruction to the LDR with the L bits in the second byte set as follows. Table 5. Byte 2 Functions of Latch Direction Register 7 L0 6 L1 Byte 2 Bit Number 5 4 3 2 L2 L3 L4 L5 1 X 0 X Time-Slot Assignment The T7570 can operate in either fixed time-slot or timeslot assignment mode for selecting the transmit and receive PCM time slots. Following powerup, the device is automatically in nondelayed timing mode, in which the time slot always begins with the leading (rising) edge of frame-sync inputs FSX and FSR. Time-slot assignment can only be used with delayed-data timing (see Figure 5). FSX and FSR can have any phase relationship with each other in BCLK period increments. Alternatively, the internal time-slot assignment counters and comparators can be used to access any time slot in a frame by using the frame-sync inputs as marker pulses for the beginning of transmit and receive time slots of 8 bits each. A time slot is assigned by a 2-byte instruction as shown in Tables 2 and 7. The last 6 bits of the second byte indicate the selected time slot from 0 to 63 using straight binary notation. A new assignment becomes active on the second frame following the end of the CS for the second control byte. The EN bit allows the PCM inputs, DR0/1, or outputs, DX0/1, as appropriate, to be enabled or disabled. Time-slot assignment mode requires that the FSX and FSR pulses must conform to the delayed-data timing format shown in Figure 5. Port Selection Two transmit serial PCM ports, DX0 and DX1, and two receive serial PCM ports, DR0 and DR1, are provided to enable two-way space switching to be implemented. Port selections for transmit and receive are made within the appropriate time-slot assignment instruction using the PS bit in the second byte. Port selection can only be used in delayed-data timing mode. Table 7 shows the format of the second byte of both transmit and receive time-slot and port assignment instructions. Note: X = don't care. Ln Bit 0 1 Interface Latch States IL Direction Input Output Interface latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the interface latch register (ILR) as shown in Tables 2 and 6. Latches configured as inputs sense the state applied by an external source, such as the off-hook detect output of a SLIC. All bits of the ILR, i.e., sensed inputs and the programmed state of outputs, can be read back in the second byte of a read of the ILR. Lucent Technologies Inc. 9 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Functional Description (continued) Programmable Functions (continued) Table 7. Time-Slot and Port Assignment Instruction 7 EN 0 0 1 1 6 PS 0 1 0 1 Bit Number and Name 5 4 3 2 T5* T4 T3 T2 X X X X 1 T1 X 0 T0 X Function Disable DX0 Output (transmit instruction) Disable DR0 Input (receive instruction) X X X X X X Disable DX1 Output (transmit instruction) Disable DR1 Input (receive instruction) Assign One Binary-coded Time Slot from 0--63 Enable DX0 Output (transmit instruction) Enable DR0 Input (receive instruction) Assign One Binary-coded Time Slot from 0--63 Enable DX1 Output (transmit instruction) Enable DR1 Input (receive instruction) * T5 is the MSB of the time-slot assignment. Transmit Gain Instruction Byte 2 The transmit gain can be programmed in 0.1 dB steps from -0.4 dB to +19.0 dB by writing to the transmit gain register as defined in Tables 2 and 8. This corresponds to a range of 0 dBm0 levels at VFXI between 0.811 Vrms and 0.087 Vrms (equivalent to +0.4 dBm to -19.0 dBm into 600 ). To set transmit gain, determine the gain required of the codec in order to achieve the overall desired transmission level point (TLP) at the PCM interface (usually 0 dBm or -2 dBm). In order for the internal hybrid-balance circuitry to be effective, the portion of VFRO returned to the codec analog input must be between -2.5 dB to -10.25 dB of the VFRO output. For instance, if a SLIC presents a -6 dBm signal to VFXI when VFRO produces 0 dBm, good hybrid balance can be achieved. If the returned signal requires amplification to satisfy this requirement, then an additional op amp in the transmit path would be required. The T7570 will accommodate the phase inversion. A spare op amp is provided in some Lucent SLICs. Once the codec gain is chosen, determine what signal level at VFXI would provide the desired TLP output at Dx. For our example of +6 dB gain (Gx) providing a 0 dBm TLP and working backwards from Dx, take the antilog of minus 6 dB divided by 20 and multiply by the 0.7746 reference level to obtain the signal level at VFXI in Vrms. As follows: (1) antilog10 (-Gx / 20) * 0.7746 = Vrms Finally, convert the signal level to a decimal number (n) using the following formula: (2) 200 * log10 (Vrms / 0.08592) = n Round n to the nearest integer and convert to binary. This is the code required by byte 2 of this instruction. Some examples are given in Table 8. Table 8. Byte 2 of Transmit Gain Instructions Bit Number 76543210 00000000 00000001 00000010 -- 1 0 1 1 1 1 1 1* -- 11000010 1 1 0 0 0 0 1 1 0 dBm0 Test Level (Vrms) at VFXI No Output 0.087 0.088 -- 0.7746 -- 0.802 0.811 * 0 dB path gain setting. Programming values greater than those listed in this table are permitted. However, large signals may cause overload. Receive Gain Instruction Byte 2 The receive gain can be programmed in 0.1 dB steps from -17.3 dB to +2.1 dB by writing to the receive gain register as defined in Tables 2 and 9. This corresponds to a range of 0 dBm0 levels at VFRO between 0.987 Vrms and 0.106 Vrms (equivalent to +2.1 dBm to -17.3 dBm into 600 ). Lucent Technologies Inc. 10 Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter low-frequency signals across a transformer SLIC, and the first-order section is intended to balance midrange to higher audio-frequency signals. As a second-order section, Hybal1 has a pair of lowfrequency zeros and a pair of complex conjugate poles. When configuring the Hybal1, matching the phase of the hybrid at low- to midband frequencies is most critical. Once the echo path is correctly balanced in phase, the magnitude of the cancellation signal can be corrected by the programmable attenuator. The second-order mode of Hybal1 is most suitable for balancing interfaces with transformers having high inductance of 1.5 H or more. An alternative configuration for smaller transformers is available by converting Hybal1 to a simple first-order section with a single real low-frequency pole and zero. In this mode, the pole/zero frequency can be programmed. Many line interfaces can be adequately balanced by use of the Hybal1 filter only, in which case the Hybal2 filter should be deselected to bypass it. Hybal2, the higher-frequency first-order section, is provided for balancing an electronic SLIC and is also helpful with a transformer SLIC in providing additional phase correction for mid- and high-band frequencies, typically 1 kHz to 3.4 kHz. Such a correction is particularly useful if the test balance impedance includes a capacitor of 100 nF or less, such as the loaded and nonloaded loop test networks in the United States. Independent placement of the pole and zero location is provided. Figure 3 shows a simplified diagram of the local echopath for a typical application with a transformer interface. The magnitude and phase of the local echo signal, measured at VFXI, are a function of the termination impedance ZT, the line transformer, and the impedance of the two-wire loop, ZL. If the impedance reflected back into the transformer primary is expressed as ZL', then the echo path transfer function from VFRO to VFXI is the following: (5) H(W) = ZL' /(ZT + ZL') Functional Description (continued) Programmable Functions (continued) To set receive gain, first determine the gain required of the codec. For line card use, determine the codec's allocation to set the overall transmission level point (TLP) at Tip\Ring accordingly (usually 0 dBm or -4 dBm). Once the codec gain is chosen, determine the signal level that would be delivered to VFRO when the reference TLP appears at DR. Take the antilog of the gain in dB (GR) divided by 20 and multiply by the 0.7746 reference level to obtain the signal level at VFRO in Vrms. As follows: (3) antilog10 (GR / 20) * 0.7746 = Vrms Finally, convert the signal level output to a decimal number (n) using the following formula: (4) 200 * log10 (Vrms / 0.1045) = n Round n to the nearest integer and convert to binary. This is the code required by byte 2 of this instruction. Some examples are given in Table 9. Table 9. Byte 2 of Receive Gain Instructions Bit Number 76543210 00000000 00000001 00000010 -- 1 0 1 0 1 1 1 0* -- 11000010 1 1 0 0 0 0 1 1 0 dBm0 Test Level (Vrms) at VFRI No Output (low Z to GND) 0.106 0.107 -- 0.7746 -- 0.975 0.987 * 0 dB path gain setting. Programming values greater than those listed in this table are permitted. However, large signals may cause overload. Hybrid-Balance Filter The hybrid-balance filter on the T7570 is a programmable filter consisting of a second-order section, Hybal1, followed by a first-order section, Hybal2, and a programmable attenuator. Either of the filter sections can be bypassed if only one is required to achieve good cancellation. A selectable 180 inverting stage is included to compensate for interface circuits that invert the transmit input relative to the receive output signal. The second-order section is intended mainly to balance Lucent Technologies Inc. The signal level returned at VFXI must be between -2.5 dB to -10.25 dB over the voice band, relative to the output at VFRO, in order for the hybrid balance function to be effective. Signals outside this range exceed the range of programmability of the hybrid path, and the software will provide unacceptable hybrid balance performance over the voice band. 11 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Functional Description (continued) Hybrid-Balance Filter (continued) VFXI TIP ZL' ZL 2.4 RVFXI - + SEL SEL 2 HYBAL2 1ST-ORDER HI FREQ. FILTER (REG 3) 1 INV ATTENUATOR GAIN SET IN REG 2 HYBAL1 1ST- OR 2ND-ORDER FILTER (REG 2) TO TX GAIN BLOCK RING ZT VFRO +2.4 FROM RX GAIN BLOCK 5-2788 (C) Figure 3. Block Diagram Hybrid-Balance Filter Network Programming the Filter On initial powerup, the hybrid-balance filter is disabled. Before the hybrid-balance filter can be programmed, it is necessary to design the transformer and termination impedance to meet system 2-wire input return loss specifications, which are normally measured against a fixed test impedance (600 or 900 in most countries). Only then can the echo path be modeled and the hybrid-balance filter programmed. Hybrid balancing is also measured against a fixed test impedance, specified by each national telecommunication administration to provide adequate control of talker and listener echo over the majority of their network connections. This test impedance is ZL in Figure 3. The echo signal and the degree of transhybrid loss obtained by the programmable filter must be measured from the PCM digital input, DR0/1, to the PCM digital output, DX0/1, either by digital test signal analysis or by conversion back to analog by a PCM codec/filter. Three registers must be programmed in the T7570 to fully configure the hybrid-balance filter (refer to Table 2 for Byte 1 addressing): Register 1: Select/deselect hybrid-balance filter; invert/noninvert cancellation signal; select/deselect Hybal2 filter section; set attenuator. 7 6 SEL INV Byte 2 of Register 1 5 4 3 2 1 0 SEL2 GAIN (All "0" = MAX) Register 2: Select/deselect Hybal1 filter; set Hybal1 to biquad or first order; select pole and zero frequency. Register 3: Program pole frequency in Hybal2 filter; program zero frequency in Hybal2 filter. Standard filter design techniques can be used to model the echo path (see Equation 5) and design a matching hybrid-balance filter configuration. Alternatively, the frequency response of the echo path can be measured and the hybrid-balance filter designed to replicate it. T7570 hybrid-balance software is available from your Lucent Account Representative to aid in selecting the best balance filter register settings. 12 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Functional Description (continued) Hybrid-Balance Filter (continued) Power Supply While the pins of the T7570 devices are well protected against electrical misuse, it is recommended that the standard CMOS practice of applying GND to the device before any other connections are made should always be followed. In applications where the printed-circuit card can be plugged into a hot socket with power and clocks already present, an extra-long ground pin on the connector should be used. To minimize noise sources, all ground connections to each device should meet at a common point as close as possible to the device GND pin to prevent the interaction of ground return currents flowing through a common-bus impedance. A power-supply decoupling capacitor of 0.1 F should be connected from this common point to VDD, as close to the device pins as possible. The power supply should also be decoupled with a low, effective series resistance capacitor of at least 10 F, located near the card edge connector. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage Voltage on Any Pin with Respect to Ground Maximum Power Dissipation (package limit) Symbol Tstg VDD -- PDISS Min -55 -- -0.5 -- Max 150 6.5 0.5 + VDD 600 Unit C V V mW Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 , capacitance = 100 pF) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained using these circuit parameters. Table 10. Human-Body Model ESD Threshold Device T7570 Voltage 2000 V Lucent Technologies Inc. 13 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Electrical Characteristics For all tests, TA = -40 C to +85 C, VDD = 5 V 5%, and GND = 0 V, unless otherwise noted. Typical values are for TA = 25 C and nominal supply values. dc Characteristics Table 11. Digital Interface Parameter Input Voltage Low High Output Voltage Low High Symbol Test Conditions VIL All digital inputs VIH All digital inputs VOL DX0, DX1, CO, IL = 3.2 mA All other digital outputs, IL = -1 mA VOH DX0, DX1, CO, IL = 3.2 mA All other digital outputs except TS X, IL = -1 mA All digital outputs, IL = -100 A Any digital input, GND < VIN < VIL Any digital input except MR, VIH < VIN < VCC MR only DX0, DX1, CO, IL5--IL0 when selected as inputs, GND < VOUT < VCC TA (C) -- -- -- -- -- -- -- -- -- -- -40 to 0 0 to 85 Min -- 2.0 -- -- 2.4 2.4 VCC - 0.5 -10 -10 -10 -30 -10 Max 0.7 -- 0.4 0.4 -- -- -- 10 10 100 30 10 Unit V V V V V V V A A A A A Input Current Low High IIL IIH Output Current in Highimpedance State IOZ Table 12. Power Dissipation Parameter Powerdown Current Symbol Test Conditions IDD0 CCLK, CI, CO = 0.4 V, CS = 2.4 V, interface latches set as outputs with no load, all other inputs active, power amp disabled IDD1 CCLK, CI, CO = 0.4 V, CS = 2.4 V, no load on power amp, interface latches set as outputs with no load Powerdown Current IDD2 CCLK, CI, CO = 0.4 V, CS = 2.4 V, interface latches set as outputs with no load, all other inputs active, power amp disabled, no load on power amp 4.0 6.0 mA Typ 0.3 Max 0.9 Unit mA Powerup Current 14.0 20.0 mA 14 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Transmission Characteristics Table 13. Analog Interface Parameter Input Resistance Input Offset Voltage at VFXI Load Resistance Load Capacitance Output Resistance Output Offset Voltage at VFRO Output Offset Voltage at VFRO, Powerdown Output Voltage Swing Symbol RVFXI VOSX RLVFRO CLVFRO Test Conditions 0.25 V < VFXI < 4.75 V -- -- RLVFRO 300 CLVFRO from VFRO to GND ROVFRO Steady zero PCM code applied to DR0 or DR1 VOSR Alternating zero PCM code applied to DR0 or DR1, maximum receive gain VOSRPD Control register byte 2, bit 7 = 0 VSWR RL = 300 , maximum receive gain Min Typ Max 390 585 -- 2.3 -- 2.5 300 -- -- -- -- 200 -- 2.3 2.3 4.01 1.6 -- -- -- 3.0 2.5 2.5 -- Unit k V pF V V VPP Table 14. Gain and Dynamic Range Parameter Absolute Levels Symbol Test Conditions GAL Maximum 0 dBm0 levels: VFXI (gain set to 11000011) VFRO (gain set to 11000011) Minimum 0 dBm0 levels: VFXI (gain set to 00000001) VFRO (gain set to 00000001) Transmit gain programmed for GXA maximum 0 dBm0 test level, measured deviation of digital code from ideal 0 dBm0 PCM code at DX0/1, TA = 25 C GXAT Measured relative to GXA, VDD = 5 V, minimum gain < GX < maximum gain GXAG Measured transmit gain over the range from maximum to minimum, calculated the deviation from the programmed gain relative to GXA (i.e., GXAF = Gactual - Gprog - GXA), TA = 25 C, VDD = 5 V TA (C) -- -- -- -- -- Min -- -- -- -- -0.15 Typ 0.811 0.987 87.0 106.0 -- Max -- -- -- -- 0.15 Unit Vrms Vrms mVrms mVrms dB Transmit Gain Absolute Accuracy Transmit Gain Variation with Temperature Transmit Gain Variation with Programmed Gain -40 to 0 0 to 85 -- -0.15 -0.1 -0.1 -- -- -- 0.15 0.1 0.1 dB dB dB Lucent Technologies Inc. 15 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Transmission Characteristics (continued) Table 14. Gain and Dynamic Range (continued) Parameter Transmit Gain Variation with Frequency Symbol Test Conditions TA (C) GXAF Relative to 1020 Hz, minimum gain < GX < maximum gain, DR0 or DR1 = 0 dBm0 code: f = 16.67 Hz -- f = 50 Hz -- f = 60 Hz -- f = 200 Hz -- f = 300 Hz to 3000 Hz -- f = 3140 Hz -- f = 3380 Hz -- f = 3860 Hz -- -- f 4600 Hz (measured response at alias frequency from 0 kHz to 4 kHz) GXAL Sinusoidal test method, reference level = 0 dBm0: VFXI = -40 dBm0 to +3 dBm0 -- VFXI = -50 dBm0 to -40 dBm0 -- VFXI = -55 dBm0 to -50 dBm0 -- Receive gain programmed for -- GRA maximum 0 dBm0 test level, applied 0 dBm0 PCM code to DR0 or DR1, measured VFRO, TA = 25 C, load = 10 k GRAT Measured relative to GRA, VDD = -40 to 0 5 V, minimum gain < GR < maxi- 0 to 85 mum gain GRAG Measured receive gain over the -- range from maximum to minimum setting, calculated the deviation from the programmed gain relative to GRA, i.e., GRAG = Gactual - Gprog - GRA, TA = 25 C, VDD = 5 V Min Typ Max Unit -- -- -- -1.8 -0.125 -0.57 -0.885 -- -- -35 -33 -40 -0.5 0.04 0.01 -0.6 -9.9 -- -30 -30 -30 0 0.125 0.125 0.012 -8.98 -32 dB dB dB dB dB dB dB dB dB Transmit Gain Variation with Signal Level Receive Gain Absolute Accuracy -0.2 -0.4 -1.2 -0.15 -- -- -- -- 0.2 0.4 1.2 0.15 dB dB dB dB Receive Gain Variation with Temperature Receive Gain Variation with Programmed Gain -0.15 -0.1 -0.1 -- -- -- 0.15 0.1 0.1 dB dB dB 16 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Transmission Characteristics (continued) Table 14. Gain and Dynamic Range (continued) Parameter Receive Gain Variation with Frequency Symbol Test Conditions GRAF Relative to 1020 Hz, DR0 or DR1 = 0 dBm0 code, minimum gain < GR < maximum gain: f 3000 Hz f = 3140 Hz f = 3380 Hz f = 3860 Hz f 4600 Hz GRAL Sinusoidal test method, reference level = 0 dBm0: DR0 = -40 dBm0 to +3 dBm0 DR0 = -50 dBm0 to -40 dBm0 DR0 = -55 dBm0 to -50 dBm0 TA (C) Min Typ Max Unit -- -- -- -- -- -0.125 0.04 -0.57 0.01 -0.885 -0.58 -- -10.7 -- -- 0.125 0.125 +0.012 -8.98 -28 dB dB dB dB dB Receive Gain Variation with Signal Level -- -- -- -0.2 -0.4 -1.2 -- -- -- 0.2 0.4 1.2 dB dB dB Table 15. Envelope Delay Distortion Parameter Tx Delay, Absolute Tx Delay, Relative to 1600 Hz Symbol DXA DXR Test Conditions f = 1600 Hz f = 500 Hz--600 Hz f = 600 Hz--800 Hz f = 800 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz f = 1600 Hz f = 500 Hz--1000 Hz f = 1000 Hz--1600 Hz f = 1600 Hz--2600 Hz f = 2600 Hz--2800 Hz f = 2800 Hz--3000 Hz Min -- -- -- -- -- -- -- -- -- -40 -30 -- -- -- Max 315 220 145 75 40 75 105 155 200 -- -- 90 125 175 Unit s s s s s s s s s s s s s s Rx Delay, Absolute Rx Delay, Relative to 1600 Hz DRA DRR Lucent Technologies Inc. 17 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Transmission Characteristics (continued) Table 16. Noise Parameter Transmit Noise, C Message Weighted, -law Selected Transmit Noise, P Message Weighted, A-law Selected Receive Noise, C Message Weighted, -law Selected Receive Noise, P Message Weighted, A-law Selected Noise, Single Frequency Symbol Test Conditions NXC All 1s in gain register NXP NRC NRP NRS All 1s in gain register PCM code is alternating positive and negative zeros PCM code equals positive one LSB Min Typ Max -- -- 15 -- -- -- -- -- -- -- -- -67 13 -79 -53 Unit dBrnC0 dBm0p dBrnC0 dBm0p dBm0 Power Supply Rejection, Transmit Power Supply Rejection, Receive Spurious Out-of-Band Signals at the Channel Output f = 0 kHz--100 kHz, analog to analog measurement (DX0 is externally connected to DR0), VFXI = 0 Vrms PPSRX VDD = 5.0 Vdc + 100 mVrms: f = 0 kHz--4 kHz* f = 4 kHz--50 kHz PPSRR PCM code equals positive one LSB, VDD = 5.0 + 100 mVrms, measured VFRO: f = 0 Hz--4000 Hz f = 4 kHz--25 kHz f = 25 kHz--50 kHz SOS 0 dBm0, 300 Hz--3400 Hz input PCM code applied at DR0 (or DR1): 4600 Hz--7600 Hz 7600 Hz--8400 Hz 8400 Hz--50,000 Hz 36 30 -- -- -- -- dBC dBC 36 40 36 -- -- -- -- -- -- dBC dB dB -- -- -- -- -- -- -30 -40 -30 dB dB dB * PPSRX is measured with a -50 dBm0 activation signal applied to VFXI. 18 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Transmission Characteristics (continued) Table 17. Distortion Parameter Signal to Total Distortion Transmit or Receive Half-channel, -law Selected Symbol STDX STDR Test Conditions Sinusoidal test method level: 3.0 dBm0 0 dBm0 to -30 dBm0 -40 dBm0 -45 dBm0 -- -- Transmit or receive two frequencies in the range (300 Hz--3400 Hz) Min 33 36 30 25 -- -- -- Max -- -- -- -- -46 -46 -41 Unit dBC dBC dBC dBC dB dB dB Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion SFDX SFDR IMD Table 18. Crosstalk Parameter Transmit to Receive Crosstalk, 0 dBm0 Transmit Level Receive to Transmit Crosstalk, 0 dBm0 Receive Level Symbol Test Conditions CTX-R f = 300 Hz--3400 Hz DR = steady PCM code CTR-X f = 300 Hz--3400 Hz* Typ -90 -90 Max -75 -70 Unit dB dB * CTR-X and PPSRX are measured with a -50 dBm0 activation signal applied to VFXI. Lucent Technologies Inc. 19 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Timing Characteristics A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purposes of this specification, the following conditions apply: s s s s s s All input signals are defined as VIL = 0.4 V, VIH = 2.7 V, tR < 10 ns, tF < 10 ns. tR is measured from VIL to VIH. tF is measured from VIH to VIL. Delay times are measured from the input signal valid to the output signal valid. Setup times are measured from the data input valid to the clock input invalid. Hold times are measured from the clock signal valid to the data input invalid. Pulse widths are measured from VIL to VIL or from VIH to VIH. Table 19. Master Clock Timing (See Figures 4 and 5.) Symbol fMCLK Parameter Frequency of MCLK--Selection Frequency Is Programmable (See Table 3.) Time of MCLK High Time of MCLK Low Rise Time of MCLK Fall Time of MCLK Hold Time, BCLK Low to MCLK High Period of FSX or FSR Low Test Conditions -- Min -- -- -- -- 80 80 -- -- 50 1 Typ 1536 1544 2048 4096 -- -- -- -- -- -- Max -- -- -- -- -- -- 30 30 -- -- Unit kHz kHz kHz kHz ns ns ns ns ns MCLK Period tMCHMCL tMCLMCH tMCH1MCH2 tMCL2MCL1 tBCLMCH tFSLFSH Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL -- Measured from VIL to VIL 20 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Timing Characteristics (continued) Table 20. PCM Interface Timing (See Figures 4 and 5.) Symbol fBCLK Parameter Frequency of BCLK (can vary from 64 kHz to 4096 kHz in 8 kHz increments) Time of BCLK High Time of BCLK Low Rise Time of BCLK Fall Time of BCLK Hold Time, BCLK Low FSX/R to High or Low Setup Time FSX/R, High to BCLK Low Delay Time, BCLK High to Data Valid Delay Time, BCLK Low to DX0/1 Disabled if FSX Low, FSX Low to DX0/1 Disabled if Eighth BCLK Low, or BCLK High to DX0/1 Disabled if FSX High Delay Time, BCLK High to TS X Low if FSX High, or FSX High to TS X Low if BCLK High High-impedance Time, BCLK Low to TS X High if FSX Low, or FSX BCLK High to TS X High if FSX High Delay Time, FSX/R High to Data Valid Test Conditions -- TA (C) -- Min 64 Max 4096 Unit kHz tBCHBCL tBCLBCH tBCH1BCH2 tBCL2BCL1 tBCLFXL tBCLFRL tFXHBCL tFRHBCL tBCHDXV tBCLDXZ Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL -- -- Load = 100 pF plus two LSTTL loads -- -- -- -- -- -- -- -- -40 to 0 0 to 85 80 80 -- -- 30 30 -- 10 15 -- -- 30 30 -- -- 90 80 80 ns ns ns ns ns ns ns ns ns tBCHTXL Load = 100 pF plus two LSTTL loads -- -- -- 60 ns tBCLTXH -- 15 60 ns tFXHDXV tDRVBCL tBCLDRX tBCLMCH Setup Time, DR0/1 Valid to BCLK Low Hold Time, BCLK Low to DR0/1 Invalid BCLK Low to MCLK High at the End of the First Data Bit Period Load = 100 pF plus two LSTTL loads, applies if FSX/R rises later than BCLK rising edge in nondelayed-data mode only -- -- -- -- -- 80 ns -- -40 to 0 0 to 85 -- 30 15 20 50 -- -- -- -- ns ns ns ns Lucent Technologies Inc. 21 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Timing Characteristics (continued) tMCH1MCH2 tMCL2MCL1 MCLK (MC) tBCLMCH BCLK (BC) tFXHBCL FSX (FX) tFXHDXV tBCHDXV DX0/1 (DX) tBCHTXL tBCHTXL TSX0/1 (TX) tFRHBCL tBCLFRL FSR (FR) tDRVBCL DR0/1 (DR) 1 2 3 tBCLDRX 4 5 6 7 8 5-2789 (C) tMCHMCL tBCL2BCL1 tBCH1BCH2 2 tBCLFXL 3 4 5 6 tMCLMCH tBCHBCL 7 tBCLBCH 8 9 1 tBCLDXZ 2 3 4 5 6 7 tBCLTXH 8 1 Note: Bit 1 = sign bit. Figure 4. Nondelayed-Data Timing Mode tMCH1MCH2 tMCL2MCL1 MCLK (MC) tBCLMCH tBCH1BCH2 BCLK (BC) 1 tBCLFXL tFXHBCL FSX (FX) tBCHDXV DX0/1 (DX) 1 tBCHTXL TSX0/1 (TX) tBCLFRL tFRHBCL FSR (FR) tDRVBCL DR0/1 (DR) 1 2 3 tBCLDRX 4 5 6 7 8 5-2790 (C) tMCHMCL tBCL2BCL1 tMCLMCH tBCHBCL 2 3 4 5 6 7 8 tBCLBCH 9 tBCLDXZ 2 3 4 5 6 7 tBCLTXH 8 Note: Bit 1 = sign bit. Figure 5. Delayed-Data Timing Mode 22 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Timing Characteristics (continued) Table 21. Serial Control Port Timing (See Figure 6.) Symbol fCCLK tCCHCCL tCCLCCH tCCH1CCH2 tCCL2CCL1 tCCLCSL tCCLCSH tCSLCCH tCSHCCH tCIVCCL tCCLCIX tCCHCOV tCSLCOV tCSHCOZ Parameter Frequency of CCLK Time of CCLK High Time of CCLK Low Rise Time of CCLK Fall Time of CCLK Hold Time, CCLK Low to CS Low Hold Time, CCLK Low to CS High Setup Time, CS Transition to CCLK Low Test Conditions -- Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL Measured from first CCLK low transition Measured from eighth CCLK low transition -- Min -- 160 160 -- -- 10 100 60 50 50 50 -- -- 15 Max 2048 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns 50 50 -- -- -- -- -- -- 80 80 80 -- Setup Time, CS Transition to CCLK High Setup Time, CI Data In to -- CCLK Low Hold Time, CCLK Low to -- CI Invalid Delay Time, CCLK High to Load = 100 pF plus 2 LSTTL loads CO Data Out Valid Delay Time, CS Low to CO Valid Delay Time, CS High to CO High Impedance Applies only if separate CS used for byte 2 Applies when CS high occurs before ninth CCLK high Table 22. Interface Latch Timing (See Figure 6.) Symbol Parameter Test Conditions tILXCCL Setup Time, IL to Eighth Interface latch inputs only CCLK of Byte 1 tCCLILX Hold Time, IL Valid from -- Eighth CCLK Low (byte 1) tCCLILV Delay Time CCLK 8 of Interface latch outputs only CL = 50 pF Byte 2 to IL Table 23. Master Reset Pin Symbol Parameter tMRHRML Duration of Master Reset High Min 1 Max -- Unit s Min 100 50 -- Max -- -- 200 Unit ns ns ns Lucent Technologies Inc. 23 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Timing Characteristics (continued) CCLK (CC) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 tCCL2CCL1 7 8 tCCLCSL tCSLCCH CS tCIVCCL CI: BYTE 1 & BYTE 2 WHEN INPUT TO CI CO: BYTE 2 WHEN OUTPUT FROM CO (CO) IL5--IL0 (IL) tCCLCIX 7 6 5 4 3 tCCHCCL tCCLCCH tCSLCCH tCCLCSL tCCH1CCH2 BYTE 2 tCCLCSH tCSHCCH 2 1 0 7 6 5 tCSLCOV tCCHCOV 7 6 5 4 3 4 3 2 tCCLCSH 1 0 tCSHCOZ 2 1 tCCLILV 0 tILXCCL tCCLILX INPUTS ONLY OUTPUTS ONLY 5-2791 (C) Figure 6. Serial Control Port Timing 24 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Applications Figure 7 illustrates a T7570 codec interfaced to a Lucent L7554 SLIC. Interface components were chosen for a basic 600 resistive only termination and balance network. Overall receive path gain is 0 dB (PCM to T/R). Overall transmit path gain is -2 dB (T/R to PCM). Codec receive gain is 0 dB. The signal level returned to VFXI is -3.658 dBm. This satisfies the transmission level point requirement for hybrid cancellation. That is, the signal at VFXI relative to the output at VFRO must be within -2.5 dB to -10.25 dB. Transmit gain of the codec is set at +1.658 dB in order to achieve a transmission level point at Dx of -2 dBm. Transmit and receive paths are capacitively coupled to accommodate different SLIC and codec bias levels. The codec's inputs are self-biased so that no additional external resistors are necessary with ac coupling. Capacitor values are sized appropriately to pass low-frequency requirements of relevant gain versus frequency templates. Resistive values were ascertained from SLIC documentation. An optional 20 k resistor from RCVN to ground and a 30 pF capacitor across RGP can be added for stability. Gain and hybrid-balance register values are shown in hex. Gain values were obtained from Tables 8 and 9. Hybridbalance values were obtained by removing the codec and inserting a network analyzer to measure the phase and gain returned by the loop to VFXI when a signal is injected at VFRO. Gain and phase are then measured at 14 frequencies. The results obtained from this exercise are plugged into the hybrid-balance software that provides the register settings as shown. L7554 CC1 0.47 F PT VITR VFXI T7570 RPT 35 TZ 600 RPT 35 RCVN PR RCVP RT1 86.6 k 2.4 V SEE REGISTER SETTINGS BELOW VFRO CRCV1 0.1 F RRCV 48.7 k RGP 20 k SLIC CODEC Register Settings Register RX GAIN TX GAIN HYBRID 1 HYBRID 2 HYBRID 3 Register Number Value 04 05 06 07 08 AE AE A4 51 88 Description 0 dB 1.658 dB -- -- -- 5-4716.a C Figure 7. 600 Resistive SLIC Interface Lucent Technologies Inc. 25 T7570 Programmable PCM Codec with Hybrid-Balance Filter Data Sheet October 1996 Outline Diagrams 28-Pin PLCC Dimensions are shown in inches. 12.57 MAX 11.58 MAX PIN #1 IDENTIFIER ZONE 4 1 26 5 25 11.58 MAX 12.57 MAX 11 19 12 18 4.57 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.53 MAX 5-2608r.4 0.10 26 Lucent Technologies Inc. Data Sheet October 1996 T7570 Programmable PCM Codec with Hybrid-Balance Filter Ordering Information Device Code T - 7570 - - - ML2 T - 7570 - - - ML2 -TR Package 28-Pin PLCC 28-Pin PLCC, Tape and Reel Temperature -40 C to +85 C -40 C to +85 C Comcode 107055782 107056525 Lucent Technologies Inc. 27 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103, 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 47 67 47 67 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1996 Lucent Technologies Inc. All Rights Reserved October 1996 DS96-223ALC (Replaces DS92-224TCOM and AY93-026TCOM) Printed On Recycled Paper |
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